1. Field of the Invention
The present invention relates to a semiconductor memory and an output signal control method and circuit in the semiconductor memory and, more particularly, to a semiconductor memory and an output signal control method and circuit in the semiconductor memory that are preferably used to prevent generation of output noise in the semiconductor memory.
2. Description of the Related Art
In a data read, a semiconductor memory including a nonvolatile semiconductor memory generally amplifies a small current flowing from a memory cell by a sense amplifier, and outputs data stored in the memory cell as an xe2x80x9cHxe2x80x9d- or xe2x80x9cLxe2x80x9d-level electrical signal through an output buffer.
FIG. 1 is a block diagram showing the first prior art of an output control circuit for controlling transfer of a signal output from a sense amplifier to an output buffer. As shown in FIG. 1, a signal output via a sense amplifier 1 through a bit line connected to a memory cell is supplied via a switching transistor 2 to a latch circuit 5 which is made up of inverters 3 and 4 and constitutes output latch unit.
The signal latched by the latch circuit 5 is supplied as data DATA to an output buffer 6. When the output buffer 6 is in an enable state, the data DATA is output as an output signal OUT through a CMOS inverter 7 made up of a p-channel transistor and n-channel transistor.
An output control signal /OE which is externally input via a control signal input terminal /OE_pin is supplied as an output buffer control signal OEB to the output buffer 6 via a control input buffer 11. When this output buffer control signal OEB is at xe2x80x9cLxe2x80x9d level, the output buffer 6 is in an enable state.
The operation of the conventional output signal control circuit having this arrangement will be described with reference to the timing chart of FIG. 2.
When an address AD changes, as shown in FIG. 2, this change is detected by an address change detection circuit (not shown), an address change detection signal ATD changes to xe2x80x9cHxe2x80x9d level for a predetermined period, and an output from a cell corresponding to the new address connected to a bit line is sensed. When the address change detection signal ATD changes to xe2x80x9cHxe2x80x9d level, a sense amplifier operation signal PD supplied to the sense amplifier 1 changes from xe2x80x9cHxe2x80x9d level to xe2x80x9cLxe2x80x9d level, and the sense amplifier 1 performs data sense operation.
When the address change detection signal ATD changes to xe2x80x9cLxe2x80x9d level, the address change detection circuit outputs a sense data reception signal LT and supplies it to the switching transistor 2. At this time, the sense amplifier operation signal PD changes to xe2x80x9cHxe2x80x9d level.
Upon receiving the sense data reception signal LT, the switching transistor 2 is turned on. The sense data DATA of the sense amplifier 1 is latched by the latch circuit 5 and supplied to the output buffer 6. The sense data DATA supplied to the output buffer 6 is output to the outside as the output signal OUT via the CMOS inverter 7.
As described above, the output buffer 6 is in an enable state when the output buffer control signal OEB supplied to its control input terminal is at xe2x80x9cLxe2x80x9d logic level.
The output buffer control signal OEB supplied to the output buffer 6 is in phase with the output control signal /OE which is externally input via the control signal input terminal /OE_pin. Hence, as shown in FIG. 2, the output buffer 6 changes to an enable state during data sense operation of the sense amplifier 1 (xe2x80x9cHxe2x80x9d-level period of the address change detection signal ATD) depending on the timing at which the output control signal /OE is externally supplied.
In this output signal control circuit, a transistor constituting the output buffer 6 has a high driving capability in order to drive an external load. If the level of the output signal OUT is inverted, the power supply potential varies. If the output signal OUT is inverted during data sense operation of the sense amplifier 1 to vary the power supply potential, large output noise is generated to destroy sense data owing to the malfunction of the sense amplifier 1 or the like. As a result, erroneous data is undesirably latched by the latch circuit 5.
In a flash memory for performing automatic algorithm operation of a write/erase, data to be output to the output buffer is switched from polling data to read data by switching the address from a given block to another block in a suspend read performed during automatic algorithm operation. At this time, if polling data and read data are switched during data sense operation of the sense amplifier 1, output noise is generated by variations in power supply potential.
FIG. 3 is a block diagram showing the second prior art, and shows the arrangement of an output signal control circuit in a flash memory. In FIG. 3, the same reference numerals as in FIG. 1 denote the same parts as in FIG. 1, and a detailed description thereof will be omitted.
In the circuit of FIG. 3, a second switching transistor 70 is interposed between a latch circuit 5 and an output buffer 6. Polling data is supplied between the second switching transistor 70 and output buffer 6 via a transistor 68. An operation switching signal POLL is supplied to the gate of the transistor 68, whereas the inverted signal of the operation switching signal POLL is supplied to the gate of the second switching transistor 70 via the inverter 69.
In the circuit of FIG. 3 having this arrangement, while the address change detection signal ATD is at xe2x80x9cHxe2x80x9d level, the operation switching signal POLL falls to xe2x80x9cLxe2x80x9d level during data sense amplifier of a sense amplifier 1, as shown in the timing chart of FIG. 4. Then, the transistor 68 is turned off to stop outputting polling data. The transistor 70 is turned on to supply an output from the sense amplifier 1 to the output buffer 6. Similarly to the first prior art, the output signal OUT is inverted during data sense operation of the sense amplifier 1, and the power supply potential varies to generate output noise. Consequently, erroneous data is undesirably latched.
In any case, in the conventional circuit, if the level of the output signal OUT from the output buffer 6 varies during sense operation of the sense amplifier 1, output noise generated by variations in power supply voltage destroys the sense data DATA of the sense amplifier 1.
To prevent the malfunction of the sense amplifier 1 under the influence of the above-described output noise, the techniques disclosed in Japanese Patent Application Laid-Open Nos. 54681/1993, 63970/1996, and 173387/1989 have conventionally been proposed.
In a xe2x80x9csemiconductor memoryxe2x80x9d disclosed in Japanese Patent Application Laid-Open No. 54681/1993, a transistor which is set off for a predetermined time corresponding to an address change is interposed between the power supply and the output point of a sense amplifier circuit. In switching the address, the output level of the sense amplifier circuit is reduced to prevent output of erroneous data even if a memory cell is erroneously selected.
In a xe2x80x9csemiconductor memoryxe2x80x9d disclosed in Japanese Patent Application Laid-Open No. 63970/1996, when output data from a sense amplifier changes, an output from the sense amplifier is disabled before an output from an output buffer is inverted. After the output from the sense amplifier is stabilized, the output from the output buffer is inverted. Variations in power supply potential by inversion operation of the output buffer hardly influences the operation of the sense amplifier. This prevents the malfunction of the sense amplifier under the influence of inversion operation of the output buffer.
In a xe2x80x9csemiconductor integrated circuitxe2x80x9d disclosed in Japanese Patent Application Laid-Open No. 173387/1989, the output time of data from a sense amplifier to an output buffer is set short until a memory cell is newly selected to output data from the output buffer after the address changes. After that, the output time is set long. This prevents output of erroneous data even if the sense amplifier or address buffer malfunctions under the influence of power supply noise generated upon outputting data to the output buffer.
In the prior art disclosed in each reference, data transferred from the sense amplifier to the output buffer is delayed by a predetermined time to reduce the influence of output noise generated when an output signal is inverted during data sense operation of the sense amplifier.
More specifically, the prior art prevents the malfunction of the sense amplifier owing to output noise generated when an output from the output buffer changes during sense operation of the sense amplifier. However, the power supply voltage varies during data sense operation of the sense amplifier depending on the timing at which the output control signal /OE is externally supplied, or the timing at which the operation switching signal POLL is supplied. The malfunction of the sense amplifier caused by variations in power supply voltage cannot be fundamentally prevented.
The present invention has been made to overcome the conventional drawbacks, and aims to prevent variations in level of a signal output from an output buffer during data sense operation of a sense amplifier, so as reliably to prevent erroneous data from being output owing to output noise generated by variations in power supply potential during data sense operation of the sense amplifier.
To achieve the above object, according to the present invention, there is provided a semiconductor memory comprising delay unit for inhibiting an output control signal, which is externally input to control the operation of an output buffer, from being transferred to said output buffer for a predetermined period after an address is changed.
According to another aspect of the present invention, there is provided a semiconductor memory including a sense amplifier and output latch unit for latching data detected by said sense amplifier, said memory comprising delay unit for inhibiting an output control signal, which is externally input to enable an output buffer, from being transferred to said output buffer until an output from said sense amplifier is received by said output latch unit.
According to still another aspect of the present invention, there is provided a semiconductor memory wherein polling data and read data are selectively switched by a polling signal and output via an output buffer in an automatic algorithm operation of a write/erase, said memory comprising delay unit for delaying data-switching based on the polling signal by a predetermined period.
According to still another aspect of the present invention, there is provided a semiconductor memory to operate by an automatic algorithm of a write/erase, comprising delay unit for delaying switching from polling data to read data while a sense amplifier performs a data sense operation in switching data from polling data to read data to be transferred to an output buffer by changing an address from a given block to another block in a suspend read performed in operating by said automatic algorithm.
According to still another aspect of the present invention, there is provided an output signal control method in a semiconductor memory, comprising the step of delaying a signal so as to inhibit an output control signal, which is externally input to control the operation of an output buffer, from being transferred to said output buffer for a predetermined period after an address is changed.
According to still another aspect of the present invention, there is provided an output signal control method in a semiconductor memory wherein polling data and read data are selectively switched by a polling signal and output via an output buffer in operating by an automatic algorithm of a write/erase, said method comprising the step of delaying data-switching based on said polling signal by a predetermined period.
According to still another aspect of the present invention, there is provided an output signal control circuit for inhibiting an output control signal, which is externally input to control the operation of an output buffer, from being transferred to said output buffer for a predetermined period after an address is changed.
According to still another aspect of the present invention, there is provided an output signal control circuit comprising delay unit for inhibiting an output control signal, which is externally input to enable an output buffer, from being transferred to said output buffer until data detected by a sense amplifier is received by output latch unit.
According to still another aspect of the present invention, there is provided an output signal control circuit wherein polling data and read data are selectively switched by a polling signal and output via an output buffer in a semiconductor memory operating by an automatic algorithm of a write/erase, said circuit comprising delay unit for delaying data-switching based on said polling signal by a predetermined period.
Even if an output control signal for activating an output buffer is externally input, the present invention having the above arrangement can keep the output buffer off for a predetermined period after the address is switched. The present invention can reliably prevent a change in logic level of the output signal owing to the output buffer changing to an enable state during a data sense operation of a sense amplifier. This can fundamentally solve the problem that output noise due to variations in power supply voltage during the sense operation of the sense amplifier is generated during the data sense operation of the sense amplifier, the sense amplifier senses erroneous data owing to a malfunction or the like, and the erroneous data is latched by the data latch circuit.
In addition, data-switching based on a polling signal in an automatic algorithm operation of a write/erase is delayed by a predetermined period. While the sense amplifier senses data, switching from polling data to read data can be inhibited effectively to prevent a malfunction caused by output-switching performed in the automatic algorithm operation.